caching controllers造句

例句与造句

1. The secondary cache controller was not integrated on the MC88110, but was located on a separate device, the MC88410, to reduce cost.
2. The leftover tag bit is instead used to store the cache line dirty bit, and all 16 Kbits in the cache controller are used for valid bits.
3. The R5000 had an integrated L2 cache controller that supported capacities of 512 KB, 1 MB and 2 MB . The L2 cache shares the SysAD bus with the external interface.
4. In 1987 it released the A38152, the world's first single-chip cache controller operating at 20 MHz and to enhance the performance of 80386-based computer systems.
5. Enhancements over Rigel included a 4 kB first-level cache and 32-bit physical memory addressing in the Mariah CPU, and write-back caching implemented in the cache controller chip.
6. It's difficult to find caching controllers in a sentence. 用caching controllers造句挺难的
7. Pentium IIs use a combined L2 cache controller / tag RAM chip that only allows for 512 MB to be cached; while more RAM could be installed in theory, this would result in very slow performance.
8. Thus, the next time the program requests T [ 0 ] to be updated, the cache misses, and the cache controller has to request the data bus to bring the corresponding cache block from main memory again.
9. This issue can be addressed in one of two ways in system design : Cache-coherent systems implement a method in hardware whereby external writes are signaled to the cache controller which then performs a cache invalidation for DMA writes or cache flush for DMA reads.
10. The CPU includes a cache controller which automates reading and writing from the cache, if the data is already in the cache it simply " appears ", whereas if it is not the processor is " stalled " while the cache controller reads it in.
11. The CPU includes a cache controller which automates reading and writing from the cache, if the data is already in the cache it simply " appears ", whereas if it is not the processor is " stalled " while the cache controller reads it in.
12. The 82497 Cache Controller with multiple 82492 Cache SRAMs combine with the Pentium processor ( 735 \ 90, 815 \ 100, 1000 \ 120, 1110 \ 133 ) to form a CPU cache chip set designed for high performance servers and function-rich desktops.
13. Two type of RAM card were available, a 4 or 8 MB card, and the " XP Cache " card, incorporating up to 8 MB with an 82385 cache controller and 32 KB of cache SRAM . Up to two memory cards could be installed, to give a maximum RAM capacity of 16 MB.
14. An 8-bit tag allows cacheing memory up to 256 times the cache size, or 64 MiB . An 11-bit tag supports up to 512 MiB . Each cache line also has a valid bit and a dirty bit, stored in the cache controller . ( 16 Kbits, or 2 Kbytes, total size .)
15. The design was spread over six chips : an integer unit ( with 16 kB instruction and 16 kB data caches ), a floating-point unit, three full-custom secondary cache tag RAMs ( two for secondary cache accesses, one for bus snooping ), and a cache controller ASIC . The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache.
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