时序验证的英文

timing verification

• 时序:    sequence; sequenti ...
• 验证:    test and verify; c ...
• 时序验证器:    verifier timing; v ...

例句与用法

1. One timing verification approach with the aid of the timing check system
   一种借助时序检测系统进行时序验证的方法
2. Based on a comprehensive research of image coding algorithm for correlation vq , novel algorithms are presented on two aspects in this paper , and corresponding vlsi coding circuit system is designed , simulated and verified
   本论文在对相关矢量量化图像编码算法进行深入分析的基础上，在两个方面提出了基于vlsi技术的新算法，并进行了vlsi硬件设计、模拟仿真和时序验证。
3. A 10 - bits system ( the result of the estimated speed is a 10 - bits digital ) and a 12 - bits one are presented and , their precisions and lc usages are compared , experimental results are given to show its effectiveness . max + plusii emulation assures the circuit structure
   本文研制了10bit和12bit两种精度的基于模型参考自适应的速度估算ip核，并进行功能和时序验证，比较了它们所占用的芯片资源的大小， max + plus的仿真确定了实际的电路硬件结构。
4. This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
   该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。