相位裕度的英文
phase margin
例句与用法
- Output buffer is realized by the feedback application of amplifier which can drive big load capacitor . the av of amplifier is more than 70db , phase - margin of it is more than 70 degree , psrr of it is more than 50db
单位增益缓冲器是具有驱动大负载电容能力的运算放大器的反馈应用,该运算放大器的增益大于70db ,相位裕度大于70度。 - 3 . a good result is gotten under the star - hspice simulation . the dc gain is 90 db , the offset voltage is 40 u v while driving 10k , the unity - gain frequency is 10mhz with phase margin 67 , the slew rate is 10w us while driving 10pf
用star - hspice仿真软件对电路仿真，在1 . 5v电源电压、直流10k负载、交流10pf负载的情况下，整个共模电压范围内跨导基本保持恒定，只有18的变化，直流增益90db ，单位增益带宽10mhz ，相位裕度80度，压摆率10v s 。 - Firstly , a two - stage structure for the ota is presented after comprehensive considerations on characteristics like open - loop gain , unity - gain bandwidth , phase margin and settling time . then the input and output topologies have been decided by comparing different structure available for this purpose
首先,通过对ota开环增益、单位增益带宽、相位裕度和建立时间等性能指标的分析,并对比了几种典型运放结构,设计开发了一种cmos全差分共源共栅两级运算放大器框架。 - Usually the low power operational amplifier is designed with rail to rail output stage , whose signal dynamirange is small , its output driving force is not strong , here it is designed with voltage displacement stage , and the strong driving force and the low power consumption in this circuit are achieved . with 5v single power , this amplifier consumes only several a , 100khz unity - gain frequency , achieves 80db dc open gain and 55 phase margin for a 100pf load capacitance and a 1m load resistance and other advantages
通常设计的低功耗轨对轨输出运算放大器中,由于信号的动态范围比较小,它的输出驱动能力不强,这里设计的是采用电平位移电路同时实现了电路的强驱动能力与低功耗,它具有在单电源电压5v的条件下,静态工作电流只有几微安,单位增益带宽达100k ,开环增益能达80db以上,相位裕度也能达55度,输出源沉电流达500微安以上等优点。
