硬件乘法的英文

• hardware multiplication

• 硬件:    hardware
• 乘法:    multiplication; 3乘11是一道容易的乘法 ...
• 硬件乘法器:    hardware multiplier
• 硬件乘法模块:    hardware multiply module
• 常数部件乘法器:    coefficient unit multiplier

例句与用法

1. The high speed mcu c8051f120 includes a multiply and accumulate engine ( mac ) which can be used to speed up mathematical operations , design control , display circuit and process data
   选用高性能单片机c8051f120 ,利用其带有硬件乘法器、运行速度高等优点,设计控制及显示电路,进行数据处理。
2. As a special element to process digital signal , the basic theory of dsp was studies internationally in 1960s , and the first general dsp chip , with a hard multiplier , was put out in 1980s
   Dsp ( digitalsignalprocessor )是一种专用的数字信号处理器。 20世纪60年代国际上开始了dsp理论基础研究， 80年代推出第一个具有硬件乘法器的通用dsp芯片。
3. Different from general microprocessors , dsps have harvard architecture or enhanced harvard architecture and units of dsps can work in parallel . to perform multiplication in high speed , dsps also include hardware multiplier in its cpu
   与通用微处理器不同，数字信号处理器采用了哈佛总线结构或改进哈佛总线结构，具有高度的并行性，为了快速完成乘法计算在cpu中增设了硬件乘法单元。
4. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ) , 5 - stage pipeline , hardware multiplier and divider , interrupt controller , 16 - bit i / o port and a flexible memory controller . new modules can easily be added using the on - chip amba ahb / apb buses . it has flexible peripheral interfaces , so can be used as an independent processor in the board - level application or as a core in the asic design
   它遵照ieee - 1745 （ sparcv8 ）的结构，针对嵌入式应用具有以下特点：采用分离的指令和数据cache （哈佛结构） ，五级流水，硬件乘法器和除法器，中断控制器， 16位的i / o端口和灵活的内存控制器，具有较强的异常处理功能，新模块可以轻松的通过片上的ambaahb / apb总线添加。