3 . the dpll completed in software was advanced based on comparing the merits and disadvantages of analog pll with that of dpll . 4 比较了模拟锁相环和数字式锁相环的优缺点，研究了一种基于软件实现的数字锁相环控制策略。
The simulation results show the method can attain our aim under harmonic condition . then the calculation errors have been analyzed 仿真结果表明，在有谐波干扰的情况下，数字锁相环方法可以准确地跟踪信号频率的变化和计算相位差。
We demonstrate the feasibility and superiority in the digital phase - locked detection applying in the life - span of the fluorescence quenching in the base of the phase - locked phase theory 锁相理论上论证了数字锁相应用于检测荧光寿命的可行性和优越性。
Create encrypted e - mail attachments that can be sent to recipients that do not have digital lock installed - only the correct password is needed to unlock encrypted files 建立加密的电子邮件附件，可以发送给收款人，不具备数字锁定装置-只有正确的密码，是需要解开加密的文件。
The application of multiple digital phase - locked technology and the high frequency complementary symmetrical pulse technology is the key content discussed in the paper 多重数字锁相技术在同步环节中的应用和本相高频互补对称脉冲技术在脉冲触发中的应用，是本文探讨的核心内容。
Benefit from the digital lock ' s ability for multiple encryption of selected files - encrypt a file more than once and use different combinations of passwords and encryption algorithms for added control 受益于数字锁定的执政能力，对于多重加密选定的文件-加密一个文件多于一次，并用不同的组合，密码和加密算法，用于新增的控制。
Secondly the theory of phased - locked loop ( pll ) is analyzed in detail , and then a method of implementing digital phased - locked loop ( dpll ) is put forward . the algorithm is well implemented using digital signal processor ( dsp ) 然后对锁相环原理进行了详细的分析，提出一种数字锁相环( dpll )的实现方法，并采用数字信号处理器( dsp )加以实现。
In this paper , we are going to use high speed digital signal processor , track the carrier wave through the digital phase locked loop , and so to demodulate the modulating signal . it can overcome the difficult problems of the other ways 而我们这里就是准备用高速数字信号处理器，利用数字锁相环实现对载波的跟踪，从而实现调制信号的解调，它能有效克服其他解调方式所遇到的困难。
Since commercial pll ic came out , phase - locked - loop frequency synthesis has become widely accepted . but when narrow frequency - step is required , the loop bandwidth has to decrease while cannot meet the demand of frequency - hopping speed 数字锁相集成器件出现以来,锁相式频率合成器得到迅速发展,但是当需要窄频率步进时,环路带宽需要降低,致使锁定时间变长,不能满足快速跳频的要求。
The results of experiment tell it is an effective method of share current . a strategy of synchronization control , which combines competition coequality and priority , is mentioned in the paper and uses digital phase - lock loop to track synchronization signal 在同步控制上，应用了“优先与抢占”的方式产生同步信号，纯硬件实现，简单可靠；使用了成熟的数字锁相环来跟踪同步信号。
