The register transfer level design with verilog hdl for the proposed architecture has been completed , and function simulation has also been accomplished in modelsim 本文对所设计的结构用verilog硬件描述语言完成了寄存器传输级设计,并使用modelsim完成了功能仿真。
And the process of functional verification consists of the implementation of rtl ( register transfer level ) simulation , gate level simulation and post - layout simulation in the process of design 验证最关键的是测试方案的制定，而功能验证的过程是在于在设计过程中实施rtl级仿真、门级仿真和后仿真。
Finally this architecture is described at the register transfer level ( rtl ) using the vhdl language . the results of simulation are identical with those of matlab simulation and thus the validity of this architecture is proved 最后用vhdl语言对各个模块进行了寄存器传输级描述,仿真结果和用matlab计算得到的结果相同,验证了设计结构的正确性。
This dissertation finishes the design of pci bus target controller , with vhdl description of register transfers level . and it has also completed the function simulation as well as timing simulation after placing & routing . a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand 本论文完成了pci总线目标设备控制器的设计，采用vhdl对其进行了rtl级的描述，并且通过编写测试激励程序完成了功能仿真，以及布局布线后的时序仿真，通过fpga在pcb实验板上进行硬件仿真，证明所实现的pci目标设备控制器符合基本功能要求。
