Nowadays , all of the microprocessor designs are often based on the superscalar technology , which has little room for improving performance more due to its two limitations : hard to realize and low resources utilization 当前的处理器主流技术超标量结构由于实现非常复杂和资源利用率低的缺陷而难以再大幅度提高其性能。
Pipelining , superscalar organization and caches will continue to play major roles in the advancement of microprocessor technology , and if hopes are realized , parallel processing will join them 在微处理器技术的发展中，流水线操作、超标量体系结构和高速缓冲内存储器仍将扮演着重要的角色。如果可能，平行处理方法也会加人。
With such research background , this dissertation focuses on the research of hardware techniques for thread level parallelism in high performance microprocessors , especially the multithreaded microprocessor which has superscalar execution core 在这种背景下，本文研究支持线程级并行的硬件技术，尤其是执行单元为超标量结构的多线程处理器。
A novel 32 bit embedded fix - point superscalar risc core is developed . then we analysis the power dissipation of risc core from view of instruction - set - architecture , datapath , supply voltage and dynamic power optimization 并从系统层次对risc处理器进行功耗分析，分别从改进指令体系结构、处理器数据通路、降低系统工作电压和动态降低功耗四个方面进行低功耗研究。
The compiler prearranges the bundles so the vliw chip can quickly execute the instructions in parallel , freeing the microprocessor from having to perform the complex and continual runtime analysis that superscalar risc and cisc chips must do 编译器预先安排好这种捆绑，因而vliw能快速地平行处理指令，免去了微处理器不得不执行复杂和连续的运行时间分析，而超级标量risc和cisc芯片必须做这种分析。
Superscalar risc microprocessor is the further development of reduced instruction set computer , it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling . this thesis anslysises the architecture and the diversified techniques of superscalar computer 超标量risc微处理器是精简指令结构( risc )的进一步发展，它通过增加并行流水执行单元并结合片上硬件动态调度来提高指令并行度。
Firstly , for the purpose of research and verification of multithread microprocessor , a superscalar microprocessor model armp - v2 is built on the basis of armp microprocessor ; secondly , the issue logic is not only the critical path in a superscalar microprocessor , but also critical to the performance of a multithreaded microprocessor with superscalar execution core 首先，在设计的嵌入式微处理armp的基础上进行改进，提出了一个超标量处理器模型，用于多线程处理器系统结构的研究与验证。其次，指令发射逻辑是超标量处理器中的关键路径，也是制约执行单元为超标量结构的多线程处理器主频提高的关键因素。
Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels . this paper present the architecture model of smpdca , and illustrated its function units , and discussed its key techniques , and analyzed the address image policy of multi - ported cache Smpdca结构具有六个突出优势：相对于大规模的超标量结构而言， smpdca结构的控制逻辑复杂性明显要低得多；相对于通过共享主存来实现处理器之间的通信的结构而言，通过一个共享的第一级数据cache来实现处理器之间的通信的smpdca结构能够提供非常小的处理器之间的通信延迟；没有cache一致性维护开销；数据cache命中率提高；便于smp (对称多处理器结构)的软件重用；从多个层次上开发程序的并行性。
To prove the feasibility of smpdca , this paper design three architecture for a chip which area is about 300 mm2 . we got performance simulation results using rsim . the results of simulation show that it is really feasible to integrate many simple microprocessors on one chip 针对smpdca结构所存在的硬件实现代价的问题，为了证明其可行性，本文以一个面积为300mm ~ 2左右的芯片的设计为目标，通过性能模拟比较，我们得出结论：在一块芯片上集成多个相对简单的微处理器是完全可行的，在硬件实现代价相近的情况下， smpdca结构可以获得比superscalar结构更优的性能。
