The main process includes following : system design , module design , function simulation , time simulation and hardware verification . the whole system is divided into several modules and each module is connected by signals , which based on the arithmetic of uart and the requirement of design . the module design is to design inner circuit structure of each module and uses verilog language to code the code 系统设计是基于uart的实现算法和设计指标要求，对系统划分模块以及各个模块的信号连接;模块设计是设计出每个模块的功能，并用verilog一hdl语言编写代码来实现模块功能;功能仿真和时序仿真使用的工具是以dence的nc _ veri109 ，首先对系统的每个模块进行功能和时序仿真，仿真通过之后，将整个系统的代码在外部的输入端口加上激励，对整个系统进行功能和时序仿真;硬件验证是用fpga对系统进行了功能验证。
In the part of platform designing , proper peripheral chips are chosen according to the audio signal format . and how to achieve channel synchronization in the receiving part is an important aspect of wireless transmission system . in order to solve this problem , three algorithms are used ; those are scramble / descramble , improved over - sampling , and frame synchronization protocol 在硬件验证平台的设计部分,文章根据音频信号的特点选择了适当的外围芯片,并且针对无线传输接收端的同步问题,采用了三种算法来减少失步现象,即扰码/解扰算法,改进型的过采样算法,以及帧同步协议。
