In this thesis two reverse - bias electrical stress methods were used to investigate the reliability of the devices . one is a typical of oc stress method with collector open and reverse - bias emitter - base junction . another one , a new technique , is fc stress method with forward - bias collector - base junction and reverse - bias emitter - base junction 本论文采用两种反偏电应力方法考察器件的可靠性，一种为传统的oc应力（集电极开路，发射结反向偏置）方法，另一种为新的方法fc应力（集电结正向偏置，发射结反向偏置）方法。
First , passive resistance network was selected as direct current biasing network , which offered direct voltage for base through the resistance voltage divider composed of two resistances , among them the upper resistance connected from the dc to base , the lower resistance connected from the base to ground . the collector connected with dc directly 直流偏置网络采用无源电阻网络，通过由两个电阻组成的电阻分压器为基极提供直流电压，上偏电阻从电源串联到基极，下偏电阻从基极到地，集电极直接加电。
A silicon self - aligned technology was achieved by using a smart power integrated technology to get high power of the circuit . vertical pnp transistor whose base is epitaxy layer was used as output . the collector of the vertical pnp transistor was set on the back of the chip with low resistance p + substrate as ohm contact 在工艺中，采用了smart功率集成技术实现电路的大功率，基区是外延层的纵向pnp晶体管作为输出，将集电极置于芯片背面，采用低电阻率p ~ +衬底作为欧姆接触。
