Design of logic control circuits , device driver and application of the high - speed data communication system based on pci bus are completed . with s5933 bus master ( dma ) , bidirectional and high - speed data transmission are realized 本文完成了基于pci总线的双机高速数据通信系统的逻辑控制电路设计、驱动程序及应用程序的开发，实现了s5933总线主控( dma )方式的双向高速数据传输功能。
In recent years , with the rapid increase of the in - voice mobile communication business , people ' s sight has already been turned to the business of the multimedia by present speech communication , the requisition on high speed data communication is more and more urgent 近年来，随着移动通信用户各类非话音业务的迅速增加，人们的视线已由现在的话音通信业务转向多媒体业务，对高速数据通信的要求越来越迫切。
The test results demonstrated the feasible of the scheme . the technique researched in this paper will largely simplify the equipment of modulation and demodulation , and may find its application in millimeter wave in high - speed data communication link 与中频调制方案和一般直接射频调制方案相比，本文所采用的技术大大简化了调制/解调设备，同时保持了优良的性能，对毫米波高速数据通信链路应用具有较大的优越性和广阔的前景。
Fifo data channel of pci interface chip s5933 and approach of realizing pci bus master dma through the fifo is introduced in detail . the reason for choosing s5933 ' s fifo to transfer data at high speed is clarified . secondly , the design process of hardware is introduced 文中首先介绍了pci总线的协议，讨论了pci接口的实现途径，并详细介绍了pci接口芯片s5933的fifo通道及其总线主控dma方式的实现方法，阐明了选用s5933的fifo通道进行高速数据通信的原因。
In some real - time systems which have mass of calculation to do and need to show the calculated results , the tasks of calculation and display are shared by two pcs in order to meet the demand for calculation speed . through high - speed data transmission , the calculated results and control command are transferred between the two pcs 在某些具有大量计算任务并需显示计算结果的实时系统中，为了满足计算速度的要求，可采用两台普通pc机并行工作，分担计算及显示任务，两pc机间通过高速数据通信完成计算结果和控制命令的相互传递。
Hardware block diagram of the pc high - speed data communication system is given . two cplds ( complex programmable logic device ) are adopted to design the logic of controlling data transmission . the process of data transmission are controlled by several foundation modules 其次，介绍了硬件设计过程，给出了pc机高速数据通信系统的硬件结构框图；在数据传输逻辑控制电路的设计上，采用了两块复杂可编程逻辑器件，通过多个功能模块实现对数据传输过程的控制，并给出了各功能模块的电路框图及verilog硬件描述语言源程序。
