内建自测试的英文

• built-in self test

• "内"英文翻译    inner; inside; within
• "建"英文翻译    build; construct; erect
• "试"英文翻译    try; test
• "内建自我测试" 英文翻译 :    built-in self test
• "内建的自测试" 英文翻译 :    bist built-in self test; bist,built-in self test
• "内建自" 英文翻译 :    bist
• "内建自动核对" 英文翻译 :    check built-in automatic
• "自测试" 英文翻译 :    self testing; selftest; self-testing
• "加电自测试" 英文翻译 :    post(power on self test
• "内置自测试" 英文翻译 :    bist built in self test; built-in self test (bist)
• "内装自测试" 英文翻译 :    bist
• "通电自测试" 英文翻译 :    power-on self test (post); poweron self testt
• "自测试程序" 英文翻译 :    self testing procedure; self-test program
• "自测试电路" 英文翻译 :    self testing circuit; self-testing circuit
• "自测试电门" 英文翻译 :    self-test system
• "自测试设备" 英文翻译 :    self-test equipment
• "自测试因数" 英文翻译 :    self-testing factor
• "自测试继电器" 英文翻译 :    self test relay; self-test relay
• "内建电流测试" 英文翻译 :    bic test
• "数据自测试程序" 英文翻译 :    data self-test program
• "自测试调制解调器" 英文翻译 :    self-testing modem
• "自动化内置自测试" 英文翻译 :    automatic built-in self-test
• "自测" 英文翻译 :    self testing; self-assessment; self-test
• "内建" 英文翻译 :    build in; builtin; exec; integrated; intrinsic
• "拉平耦合器自测试表" 英文翻译 :    flare coupler self-test meter

• The pseudorandom test pattern generation for bist
  基于内建自测试的伪随机测试向量生成方法
• Bult - in self - test is considered to be the most hopeful technology to solve the great cost and difficulty of manufacturing test because of the increasing of the circuit density
  内建自测试( buit - in - self - test ， bist )技术被认为是解决由于电路集成度越来越大所造成的测试费用巨大和测试访问困难等问题的最有希望的技术。
• In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result , the fault coverage is more than 96 %
  本文针对嵌入式微处理器estar1的结构特点，研究并实现了边界扫描、内部全扫描和内建自测试三种可测性设计技术，取得了良好的效果，故障覆盖率达到96以上。
• Not only the scan route solution , the built - in self - test solution and the boundary scan solution of design for testability are summarized , but also the applications and countermeasures of these 3 solutions are analysed and compared in details
  摘要综述了超大规模集成电路的几种主要的可测试性设计技术，如扫描路径法、内建自测试法和边界扫描法等，并分析比较了这几种设计技术各自的特点及其应用方法和策略。
• The advantages of the two methods are combined together in the pseudo - random current injection testing method , which improves the efficiency and correctness of the test , and which is much more operable , thus it is very applicable in built - in - self - testing of analog and mixed signal circuits in system chips
  伪随机注入电流测试法结合了两种方法的优点,提高了测试的效率和正确性,实现时简单易行,非常适合于系统芯片中对模拟及混合信号电路的内建自测试。
• In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future
  第五章提出了基于ieee754浮点标准的浮点运算处理器的设计和异步串行通信核的设一浙江大学博士学位论文计，提出了适合硬件实现的浮点乘除法、加减运算的结构，浮点运算处理器主要用于高速fft浮点处理功能，异步串行通信核主要用于pft处理器ip核的外围扩展模块以及本文所做的验证测试平台中的数据接口部分第六章提出了面向系统级芯片的可测试性设计包括了基于扫描测试atpg 、内建自测试bist 、边界扫描测试jtag设计，在讨论可测试性设计策略选择的问题上，提出了针对不同模块进行的分别测试策略，提出了层次化jtag测试方法和扫描总线法，提出了基于fpga
• And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths . boundary scan is designed according to ieee1149 . 1 , and some other instructions such as degug , runbist are provided to support internal fault testing , online debugging and built - in self - test besides the several necessary insructions . internal scan is implemented by partial scan , through this the boundary of logic component and user - cared system registers can be selected to be scanned
  Bist用于测试cpu的微码rom ,其它ram则利用微码rom中的微程序进行测试,而微程序的运行则可以顺带覆盖其它数据通路,从而使高达70 %的硬件得到测试;边界扫描按ieee1149 . 1标准设计,除必备的几条边界扫描指令外,还提供了debug 、 runbist等指令以支持内部故障测试、在线调试及内建自测试;内部扫描采用部分扫描策略,选择逻辑部件的边界及用户关心的系统寄存器进行扫描,从而实现了硬件逻辑划分,方便了后续的测试码产生和故障模拟,并为在线调试打下了基础。
• Otherwise , as a memory component , large - scale register file holds a large number of data , so it requires stronger stability and validity . for memory components , using bist method to make a fault checking is a relatively good choice . but the bist of the multi - port register file is still in early phase of development
  另外作为存储部件,规模大的寄存器文件现场保存量大,需要有很强的稳定性和正确性,而内建自测试是存储部件进行故障检测的较佳选择;但是多端口寄存器文件的测试却处在初始发展阶段,故障模型和测试算法都有待于进一步完善。
• Using “ logical effort ” method to analyze the circuit ’ s critical path , and choose the optimized size of transistors in theory by this method . then , using sta technique simulates and analyzes the circuit to optimize transistors size further , and the circuit optimization arithmetic based on sta is gained . results proved that the optimization strategy of combining theory and practice have better effect
  结果证明,这种理论与实际结合的优化策略具有较好的效果;三、典型条件下,所实现版图关键路径延时1 . 38ns ,平均功耗45 . 3mw ,版图面积0 . 05112mm2 ,达到了较小的延时、功耗和面积;四、针对所设计的算术逻辑部件,研究了一种独特的内建自测试方法,只需较少的测试向量就可实现该部件100 %的故障覆盖率,具有很高的效率和较低的代价。

• 内建自测试的法语：Built-in self-test
• 内建自测试的韩语：내장 자체시험