可测性设计的英文

• design for testability，dft

• "可"英文翻译    approve
• "测"英文翻译    survey; fathom; measure
• "性"英文翻译    nature; character; dispositi ...
• "设计"英文翻译    devise; project; plan; desig ...
• "可测试性设计" 英文翻译 :    design for testability
• "面向可测试性设计" 英文翻译 :    design for testability
• "可测性" 英文翻译 :    measurabilitymensurabilitytestability; testability
• "测试与可测试性设计" 英文翻译 :    testing and testable design of vlsi systems
• "b可测性" 英文翻译 :    b measurability
• "可测性状" 英文翻译 :    measurable character
• "强可测性" 英文翻译 :    strong measurability
• "性设计" 英文翻译 :    reliability design rd; reliability design, rd
• "可追踪的不可测性" 英文翻译 :    traceable uncertainty
• "代表性设计" 英文翻译 :    representative design
• "弹性设计" 英文翻译 :    elastic design methld
• "方案性设计" 英文翻译 :    conceptual design
• "概念性设计" 英文翻译 :    conceptual design
• "刚性设计" 英文翻译 :    rigid design; rigid type design
• "回收性设计" 英文翻译 :    design for recycle
• "经验性设计" 英文翻译 :    experimental design
• "可靠性设计" 英文翻译 :    design for reliability; reliability design, rd
• "可行性设计" 英文翻译 :    feasibility design
• "耐波性设计" 英文翻译 :    design for seakeeping
• "实验性设计" 英文翻译 :    design for experiment
• "试验性设计" 英文翻译 :    experimental design

• Design of high - frequency local source of very small aperture terminal
  高频锁相环的可测性设计
• Application and analysis of the scan path in asic ' s testable design
  可测性设计中扫描路径的应用与分析
• Dft for high - frequency pll
  高频锁相环的可测性设计
• Application of boundary scan technique to the design for board - level test
  边界扫描技术在板级可测性设计中的应用
• Design for testability means adjusting the structure of circuit and making the circuit easy to test
  可测性设计即调整电路的内部结构，使电路变得易测。
• By using design for testability , we can abridge the contriving period and reduce the cost
  对电路进行可测性设计，将缩短产品的开发周期、降低产品的开发成本。
• A plan of design for test based of boundary scan testing is introduced for this signal processing system
  接着，提出了该信号处理系统基于边界扫描的可测性设计方案。
• This paper presents an effective design ? for ? testability and test scheme for ( fft ) processor
  针对快速傅里叶变换处理器，本文提出了一种有效的可测性设计及其测试方案。
• The subject of this dissertation is the research on the design for testability in the design environment of system on a chip
  本论文的研究课题为片上系统（ systemonachip ，简称soc ）环境下的可测性设计方法学研究。
• In order to allay the difficulty of test , one should pay attention to the design for testing ( i . e . dft ) during the period of system design
  为了减少测试的困难，人们普遍接受的途径是在设计过程中注意到电路的可测性，即所谓可测性设计。