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总线仲裁的英文

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"总线仲裁"怎么读用"总线仲裁"造句

英文翻译手机手机版

  • bus arbitration

例句与用法

  • Detail specification for type j 82289 bus arbiter of semiconductor integrated circuits
    半导体集成电路j 82289型总线仲裁器详细规范
  • The scheduling policy of the bus arbitration unit was been analyzed and the i / o function of rtos was partly implemented in hardware
    本文在分析总线仲裁单元的时间片调度的基础上,将操作系统的i o管理的功能部分采用硬件实现。
  • In hardware design , a storage bus arbiter with a scalable interface for data acquiation channels was realized by fpga ( field programmable gates array ) , by which multi daq channels were supported
    本系统的硬件设计中,利用fpga设计了包含可扩展的数据采集通道接口的存储总线仲裁逻辑,支持多通道数据采集。
  • 3 . realize the interface between pci9054 and the pci bus , including the bus arbitration , read and write of the registers , the configuration of the eeprom , the dma transfer , interrupt response and so on
    3 .实现pci9054与计算机pci总线的接口,包括总线仲裁,寄存器读写操作, eeprom的配置和下载, dma传输,中断响应等功能。
  • The bue can has the functions of in polysleeve way , non - destructive bus arbitration technigue , super - strong - error measurement and high communication rate etc . which have been widely used in the various low cost , high anti - interference multi - machine systems
    Can总线以其多主方式、非破坏性总线仲裁技术、超强错误检测和高通信速率等功能在各种低成本、高抗干扰的多机系统中得到了广泛应用。
  • Emphatically introduce the can communication protocol in user layer based on multi - host competition and bus arbitration , and state the distribute software mechanism which applies the vxd ( virtual x device ) technology which work in ringo of the windows operation system to realize the real - time control of the robotic excavator
    着重阐述了基于多主竞争和总线仲裁的命令加参数的can高层通信协议的制定和为实现机器人实时控制而采用的以vxd (虚拟设备驱动程序)为核心的分层分布式软件体系结构。 4 、展示挖掘机器人分布式控制系统的运行状况。
  • Two 3 - frames - grained scheduling policies are suggested to make good trade - off between processing demands and on - chip buffer demands in software decoding implementation . a static time division multiplexed scheduling / dynamic fixed priority arbitration based 2 - level hybrid arbitration scheme , incorporated with synchronization control , is introduced in this paper to utilize the bus bandwidth effectively and lower on - chip buffer demands in media soc
    提出了一种基于静态分时复用调度动态固定优先级仲裁的混合二级总线仲裁策略,通过分割总线时间片静态调度媒体数据流dma传输,使之与解码流程同步配合,有效地分配和使用总线带宽,降低了片上数据缓存等硬件开销。
  • Especially , the idea of constructing cycle fifo in the design of reading / writing of ip core is put forward and implemented ; in the design of pci bus arbitration mechanism , in order to overcome the regular pri algorithm " full and hungry uneven drawback " , a pci arbitrate algorithm based on rotational pri is proposed and implemented which can support six pci devices ' s bus arbitration
    其中,在ip核的读/写fifo设计中,提出构建循环fifo行的思想,并进行了实现;在pci总线仲裁机制设计中,为了克服固定优先级算法“饱饿”不均的弊端,提出并实现了一种基于循环优先级的pci仲裁算法,该算法能够支持六个pci设备的总线仲裁。
  • Then the designs of modules mentioned in the scheme are discussed in detail . the main contents of the dissertation include : 1 . to satisfy the need of a16 / d16 single - cycle and block data transfer capability , the method of the state machine and diagram are adopted . the arbiter , requester , interrupter , interrupter handler modules are also implemented by use of the state machine . these modules are verified theoretically by using timing simulation
    本文具体工作如下: 1 .用状态机和电路图的方式实现了vme总线a16 / d16单周期数据读写和块传输功能;并用状态机设计了vme总线请求器,总线仲裁器,中断器和中断处理器等,并进行了时序仿真。
  • During the design of vxi - bus serial controller module , the functions of vxi - bus including time - sequence for vxi interface , resource management , interrupt process , bus arbitration , are accomplished . to advance the performance and stability , the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence , the uart , the parameterized baud generator and “ pipeling frame ” . the handle type of data transfer bus for vxi - bus is researched thoroughly , and the format of serial data transfer is designed
    在vxi总线串行控制器设计中,实现了vxi总线控制器的基本功能,包括vxi总线接口时序、总线仲裁、超时处理等;同时利用先进的fpga技术实现了串行总线时序向vxi总线时序的转换、通用异步收发器( uart ) 、参数化波特率发生器、流水线结构等功能模块;在设计中还深入研究了vxi总线数据传输的各种操作类型,制定了串行数据传输的编码格式。
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