扫描链的英文

• scan chain

• "扫描"英文翻译    scan; scanning; scansion; sw ...
• "链"英文翻译    chain
• "边界扫描链" 英文翻译 :    boundary-scan chain
• "扫描" 英文翻译 :    scan; scanning; scansion; sweep; exploring 行扫描 line scanning; 飞点扫描 flying-spot scanning; 扫描范围 scanned area; 扫描方法 scan method; 扫描方式 scanning mode; scanning method; 扫描方向 scanning direction; scanning track; direction of scanning; 扫描放大器 [电子学] sweep amplifier; scanning amplifier; scanner amplifier; 扫描幅度 scan amplitude; sweep amplitude; 扫描辐射计 scanning radiometer; 扫描辐射仪scanning radiometer; 扫描干扰 [电子学] scanning interference; sweep jamming; 扫描干涉仪 scanning interferometer; 扫描技术 scanning technique; 扫描计数器 scan counter; 扫描记录 sweep record; 扫描记录仪 scanning recorder; 扫描器 scanner; scanister; scanning apparatus; scanning device; 扫描天线 scanning antenna; 扫描头 [电子学] probe; scanning head;扫描投影仪scanning projector; 扫描透镜 scanning lens; 扫描装置 [工业] scanner; sweep unit; time-base unit; scanister; scanning unit
• "全扫描, 满扫描" 英文翻译 :    full scan
• "扫描仪，扫描器" 英文翻译 :    scanner
• "帧扫描,场扫描" 英文翻译 :    field scan
• "帧扫描,纵扫描" 英文翻译 :    frame scan
• "a型扫描" 英文翻译 :    a-mode scanning; a-scan
• "ct扫描" 英文翻译 :    ct scanning
• "emi扫描" 英文翻译 :    emi scan
• "j扫描" 英文翻译 :    j-scan
• "k扫描" 英文翻译 :    k scan; k-scan
• "pet扫描" 英文翻译 :    pet scan
• "暗扫描" 英文翻译 :    scanning in darkness
• "表扫描" 英文翻译 :    table scan
• "场扫描" 英文翻译 :    feld time-base; field sca ing; field scanning; field sweeping; field swept; field-sweep; field-swept; frame scanning; vertical scan
• "长扫描" 英文翻译 :    long-sweep
• "超扫描" 英文翻译 :    super scanning
• "磁扫描" 英文翻译 :    magnetic scanning
• "粗扫描" 英文翻译 :    coarse scanning
• "单扫描" 英文翻译 :    scan odd; single sweep; singlesweep
• "点扫描" 英文翻译 :    spot scan
• "电扫描" 英文翻译 :    electric scanning; electrical scanning; electrical sweep
• "肺扫描" 英文翻译 :    lung scan; pulmonary scan

• Yu hu , yinhe han , huawei li , tao lv , and xiaowei li , " pair balance - based test scheduling for socs " ， in : proc . of ieee asian test symposium ( ats ) , nov . 2004 , pp . 236 - 241
  董婕，胡瑜，韩银和，李晓维， "基于组合解压缩电路的多扫描链测试方法" ，计算机研究与发展，已录用。
• Otherwise , by using some board - level test theories and methods , a test resolution , including bst infrastructure integrity test , interconnect test and cluster test was given
  另外,结合板级测试的相关理论和方法,提出了一套板级测试解决方案,包括扫描链完整性测试、互连测试和簇测试。
• Based on the addition algorithm , the design was optimized by the method of scan chain control and iterative invoke and realized 14 kinds of large - number operations such as addition , subtraction , multiplication , division , module addition , module multiplication , module exponential , etc
  基于简单的加法操作，采用扫描链控制、迭代调用等方法对设计进行优化，实现了14种基本的大数运算功能。
• First , the low testing power dft solution - - scan array architecture are presented . in the scan array , the inserted wrapper and paralleled leaf scan chain reduce the testing power as low as the power dissipation in the normal working mode
  首先，从优化测试功耗的角度出发提出了扫描阵列结构，通过加入wrapper测试控制结构以及构建并行化的分支扫描链，有效地将测试功耗降低到与正常工作功耗相当的量级。
• Chapter two detailedly presents the design of the boundary scan testing system which is in accordance with ieee . 1149 . correspondingly two special - used data registers are added , one of which is the scanning chain register and the other is the child scanning chain control - register
  文中第二章按照ieee . 1149标准详细设计了边缘扫描测试系统，相应增加了两个专用数据寄存器，其中一个为扫描链寄存器，一个为扫描子链控制寄存器。
• During test , some registers in the processor are converted into scan chains to improve controllability of the circuit , the adders in the processor are used as test generators , and the produced test patterns can detect any combinational faults within every basic building cell of fft processor
  测试时，该方案将处理器中的寄存器作为扫描链提高了其可控性，利用其中的加法器作为测试生成，生成的测试矢量能侦测处理器每个基本组成单元内部的任意组合失效。
• After that , it introduces the design for test techlonogy in this chip and some valuable and important methods of debugging and testing for both the chip and fpga systems . the main contributions of this paper are discussing the core algorithms in post - process chip and their implementations in asic . it also proposes some constructive ideas of the debugging and testing of the asic and fpga systems
  另外，在芯片的可测试性方面，创造性地提出了利用芯片内部的扫描链进行功能故障测试的思想；在fpga系统的调试方面，创造性地提出来利用计算机并口的epp模式构建测试平台的思想，同时把这两种思想成功运用于芯片测试和验证中。