操作时序的英文

• time sequential routine
• timesequentialroutine

• "操作"英文翻译    operate; manipulate; handle
• "时序"英文翻译    sequence; sequential; time s ...
• "工作时序" 英文翻译 :    work schedule
• "非时序操作" 英文翻译 :    non sequential operation; nonsequential operation; nonsequentialoperation
• "时序操作" 英文翻译 :    sequential operation
• "操作时间" 英文翻译 :    hours on stream; hours to stream; manipulation time; operating time; operation time; operator; running time; time in activity
• "操作时数" 英文翻译 :    operation hours
• "可操作时间" 英文翻译 :    operational time
• "试操作时间" 英文翻译 :    time to manoeuver
• "操作时间, 工作时间" 英文翻译 :    operate time
• "链式时序操作" 英文翻译 :    cso chained sequential operation
• "自动时序操作" 英文翻译 :    automatic sequential operation
• "标准操作时间" 英文翻译 :    standard operation time; standard poeration time; standard working time
• "操作时的镇静" 英文翻译 :    procedural sedation
• "操作时限已过" 英文翻译 :    session failed
• "超载操作时间" 英文翻译 :    overload operating time
• "规定操作时间" 英文翻译 :    scheduled operating time
• "连续操作时间" 英文翻译 :    power lifetime
• "每炉操作时间" 英文翻译 :    tap to tap time
• "平均操作时间" 英文翻译 :    average operating time; average operation time
• "人工操作时间" 英文翻译 :    handing time
• "系统操作时间" 英文翻译 :    system operating time
• "延续操作时间" 英文翻译 :    continuous operation time
• "预定操作时间" 英文翻译 :    scheduled operating time
• "正常操作时间" 英文翻译 :    normal working time

• After the designing was finished , the instruction system and operating scheduling were given
  设计完成后，给出了单片机的各种操作时序以及指令系统。
• On the base of investigating the properties of pci address / data bus and the sequence of read , a re - use model of pci address / data bus is proposed
  讨论了pci接口ad双向总线及pci接口读操作时序的特性。提出了pciad总线再复用模型。
• Based on the realization of the encoder / decoders , this scheme aims at the highest rate downstream frame , and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation . the fprme decoder is advanced in the world . the parallel fec circuit completely conforms to the itu - t protocols , and has important practical value
  在rs ( 255 , 239 )硬件编码器/解码器实现的基础上,本文按照gpon协议要求,针对gpon中最高速率2 . 488gbps的下行帧,通过设计复杂的操作时序,实现了符合协议规定的32位并行fec编解码和解扰码电路,并作了仿真。