方块电阻的英文

• ohms per square
• sheet resistance

• "方块"英文翻译    diamond; block
• "电阻"英文翻译    resistance; electric resista ...
• "大块电阻器" 英文翻译 :    bulk res1stor
• "方块" 英文翻译 :    diamond; block
• "单块电路" 英文翻译 :    monolithic circuit
• "淀粉块电泳" 英文翻译 :    starch block electrophoresis
• "硅单块电路" 英文翻译 :    silicon monolithic circuit
• "模块电源" 英文翻译 :    dc-dc ac-dc
• "棋块电路" 英文翻译 :    modular circuit
• "一块电子表" 英文翻译 :    a digital watch
• "子块电算" 英文翻译 :    blockette
• "组块电源" 英文翻译 :    fabricated electric source
• "单块电路设计" 英文翻译 :    monolithic layout
• "二次模块电源" 英文翻译 :    secondary power module
• "电阻" 英文翻译 :    (物质阻碍电流通过的性质) resistance; electric resistance (电路中两点间在一定压力下决定电流强度的一个物理量)◇电阻表 ohmmeter; resistance card; ohm gauge
• "长方块" 英文翻译 :    oblong block
• "方块；积木" 英文翻译 :    block
• "方块冰" 英文翻译 :    cube ice
• "方块料" 英文翻译 :    brick
• "方块牌" 英文翻译 :    playing card
• "方块体" 英文翻译 :    quadrate
• "方块图" 英文翻译 :    black diagram; block chart; block diagram; blockdiagram; functional diagram; skeleton diagram
• "方块五" 英文翻译 :    the five of diamonds
• "方块舞" 英文翻译 :    square dance
• "方块物" 英文翻译 :    quadrate

• The transmittance and reflectance properties of different sheet resistance ito films have been researched in this paper
  研究了不同方块电阻ito膜的透射和反射特性。
• The result is showed that the value of square resistence is 30 . 2 o in heavily doping area and 100 . 2o in lightly doping area
  实验结果显示，重掺杂区和轻掺杂区的平均方块电阻分别为30 . 2和100 . 2 ，相差70 。
• A detailed analysis of the electrical properties of ato thin films was carried out in order to investigate the sb / sn atomic ratio and substrate temperature ' s influence on the ato thin film . a convictive explanation brought forward to illustrate the changing of the electrical ； properties of the ato thin film in different conditions
  在温度较低时( < 500 ) ，薄膜的方块电阻随成膜温度的升高而降低；当基板温度继续升高，薄膜的方块电阻随基板温度的升高而增大，这主要是因为玻璃基板中k ~ + 、 na ~ +离子向薄膜中的扩散。
• Secondly , we measured the electrical properties of the ion - implanted samples by hall method ( square carrier concentration , square resistance and carrier mobility ) . after comparing and analyzing , we can know that the electrical properties were affected by the difference of mn dose , the implantation of c and the annealing temperature
  其次，利用霍尔测试方法测量了每种离子注入样品的电性质(方块载流子浓度、方块电阻及载流子迁移率) ，通过比较分析了解到mn元素注入剂量、 c元素的注入以及退火温度的不同，都会对样品的电性质产生影响。
• Experimental results revealed that the carrier mobility increased with increasing of the annealing temperature , in the range of the annealing temperature from 650 ? to 850 ? , which implied that the crystal lattice structure was damaged by ion implantation and restored after annealing . furthermore , the square carrier concentration decreased , and the square resistance of the samples implanted by mn + and c increased with the raising of annealing temperature . these results indicated that the second phase such as mnga , mnas ferromagnets was formed by more mn + ions with increasing of the ( gaas ) annealing temperature , so the mn + ions which can provide carriers decreased
  由实验结果可以知道在退火温度为650 850范围内，样品的载流子迁移率随着退火温度的提高呈上升趋势，说明杂质元素的注入对样品造成晶格损伤，但退火对这些损伤具有修复作用；此外，随着退火温度的上升，样品的方块载流子浓度不断下降，加c样品的方块电阻不断上升，这都是因为随着退火温度的提高，掺入的mn ~ +离子不再提供载流子，而是形成了mnga 、 mnas等磁性第二相。
• The films prepared under 425 ? is composed with amorphous snoi and its sheet resistance is very high . with the substrate temperature ' s increasing , the degree of crystallization , film thickness increase and electrical resistivity , sheet resistance decrease obviously . when the substrate temperature is higher than 525 ? , the temperature ' s increasing is not of benefit to the films thickness and sheet resistance
  常压热分解cvd法制备的sno _ 2在较低基板温度下制备出的薄膜基本上是非晶态的，方块电阻很高；随着基板温度的升高，薄膜厚度增加，薄膜结晶程度提高，薄膜电阻率和方块电阻均显著降低；当基板温度高于525以后，随着基板温度的升高，薄膜厚度基本不再明显增加，薄膜结晶程度继续提高，薄膜电阻率继续降低，方块电阻不再明显降低。
• The traditional bandgap reference circuit was improved in the design , which includes the applying of self - bias structure and cascode structure , output of the opamp was used as self - bias voltage , saving bias circuit , and then it was helpful to get low power consumption . through using poly resistance of high value with low temperature coefficient , we reduced the influnce to circuit , if power supply did not change , we must decrease operating current to decrease power consumption , and increasing value of resistor could decrease the operating current efficiently . poly resistance of high value had large value of squared resistor , so we could save layout area
  对传统带隙基准电路进行了改进设计,采用自偏置结构和镜像电流镜结构,利用运放的输出电压作为运放的偏置电压,节省了偏置电路,降低了功耗;使用低温度系数的多晶硅高值电阻,降低了电阻温漂对电路的影响;在电源电压不变的情况下,为了减小功耗就必须减小工作电流,而增大电阻的阻值能有效地减小工作电流,多晶硅高值电阻的方块电阻很大,可以节省版图面积。
• Through study on the electrical performance of sn - in2o3 nano powder , some conclusions were drawn . when sn - in2o3 precursor was calcinated at 700 - 1000 , low square resistance was got . the resistance was lower when sn - in2o3 precursor was calcinated in vacuum than air condition
  Sn - in _ 2o _ 3纳米粉体的电性能研究表明： sn - in _ 2o _ 3前驱物在700 - 1000煅烧，方块电阻较低，真空条件下煅烧试样的电阻比空气条件下煅烧试样的电阻低，南京工业大学硕士学位论文中文摘要sno :掺杂10wt %左右时，试样方块电阻最低。