时钟抖动的英文

• clock jitter
• jitter

• "时钟"英文翻译    clock
• "抖动"英文翻译    shake; tremble; vibrate; cha ...
• "低抖动时钟" 英文翻译 :    clock lowjitterr; clock, low-jitter; low-jitter clock
• "抖动" 英文翻译 :    (颤动; 用手振动)1.shake; tremble; vibrate; chatter 在风中抖动的帆 sails shaking in the wind; 她伸出手拿乐器时, 手微微有些抖动。 her hands trembled slightly as she reached for the instrument.2.agitation; joggling; whipping; flutter; jitter; jarring
• "时钟" 英文翻译 :    [电学] [半] clock◇时钟计数器 [自动化] clock counter
• "颤抖；抖动" 英文翻译 :    quiver v. slightly tremble
• "抖动,颤抖" 英文翻译 :    whipping
• "抖动板" 英文翻译 :    oscillating deck; saddle board; shaker pan; shaking board; shuttle board; tossing board
• "抖动的" 英文翻译 :    whipping
• "抖动杆" 英文翻译 :    vibrating boom
• "抖动焊" 英文翻译 :    whipping welding
• "抖动盒" 英文翻译 :    l ditherbox
• "抖动框" 英文翻译 :    dithebox
• "抖动率" 英文翻译 :    wow flutter
• "抖动器" 英文翻译 :    kicker; stirrer
• "抖动色" 英文翻译 :    dithered color
• "抖动筛" 英文翻译 :    grading shoe; shaker riddle; shaker shoe; traveling sieve; travelling sieve
• "抖动声" 英文翻译 :    whipping
• "抖动轴" 英文翻译 :    shaker shaft
• "摇动，抖动" 英文翻译 :    shake-out
• "δ时钟" 英文翻译 :    delta clock
• "报时钟" 英文翻译 :    speaker clock; time bell; time signal clock
• "从时钟" 英文翻译 :    slave clock
• "点时钟" 英文翻译 :    dclk(dot clock
• "定时钟" 英文翻译 :    time clock; timing clock; timing watch; traceable timer

• Timing jitter in satellite data modem
  卫星数字调制解调器中的时钟抖动
• Clock jitter measurement technique based on signal - to - noise ratio
  基于信噪比测量时钟抖动的方法
• Figure 5 . 36 shows the relationship between sampling clock jitter and snr previously presented
  图5 . 36显示了采样时钟抖动和信噪比之间的关系。
• The result shows that the parameter - estimating method can measure not only the value of jitter , but also its distribution
  结果表明，采用参数佑计测量法测量时钟抖动，不但能够准确地测出抖动的大小，而且能够测出抖动的分布。
• Based on all these above , two schemes which use digital methods to measure the jitter of a pll clock of 2 . 048mhz are presented and accomplished
  在此基础上，提出并实现了测试一固定频率（ 2 . 048mhz ）锁相时钟抖动的方案。
• Dba design can enhance the dll circuit ' s robustness and minimize the clock jitter . it also avoids the difficulty of analog parameter design and process control
  采用这样的设计，增加了dll电路的稳定性，减小了时钟抖动，同时避免了模拟电路参数设计和工艺控制的难点。
• At the same time , the influence of the parameter - estimating error and the noise on amplitude of the signal are discussed , and simulation was performed to validate the analysis result
  同时，还从理论上分析了参数估计误差和信号幅度噪声对测量时钟抖动的影响，并进行了仿真验证。
• The effects of sampling clock jitter on signal - to - noise ratio ( snr ) and effective bit ( enob ) performance discussed in section 3 are even more dramatic in undersampling applications because of the higher input signal frequencies
  在第三章讨论的采样时钟抖动对信噪比和有效位性能的影响在欠采样应用中因为更高的输入信号频率显得更有戏剧性。
• It was satisfied for performance testing of high - speed a / d circuit in the project assess the factors of reducing a high speed a / d circuit performance were found out , such as harmonic distorted in front analog circuit , . sample clock shaking , analog power and the noise in ground plane etc
  并在试验测试的基础上找出了影响高速模数转换电路转换性能的几个主要的因素，即：前端运放电路谐波失真、采样时钟抖动、模数电源及共地噪声串扰等。
• The relationship between the clock jitter and the sampling sequence of a sine wave is studied , and a new method to measure the jitter and distribution of a clock signal with pico - second resolution is proposed using adc sampling based on estimating method of the parameters in sine signal
  摘要研究了时钟抖动与正弦信号的采样序列之间的关系，并在正弦信号参数估计法的基础上，提出一种利用adc采样测量皮秒量级的时钟抖动大小和分布的新方法。