模块逻辑的英文

• module logic

• "逻辑"英文翻译    logic
• "分块逻辑" 英文翻译 :    partitioned logic
• "块逻辑设计" 英文翻译 :    block logic design
• "块逻辑计算机" 英文翻译 :    block logic computer
• "逻辑模块" 英文翻译 :    logic module; logical module
• "逻辑模块，逻辑组件" 英文翻译 :    lm logic module
• "通用逻辑模块" 英文翻译 :    ulm universal logical module; universal logic module
• "可编程序逻辑模块" 英文翻译 :    programmable logic module
• "逻辑模块标识符" 英文翻译 :    lmid logical module identifier
• "模块化逻辑语法" 英文翻译 :    modular logic grammar
• "内建逻辑模块监测" 英文翻译 :    built-in logic block observation
• "可编程逻辑阵列模块" 英文翻译 :    lab
• "模块" 英文翻译 :    camac module,camac; die block; die bottom; distributed i/o modules; ethernet i/o modules; fieldbus i/o systems; gps; import vb module; industrial i/o; ipm; lcm; model block; rs-i/o modules; samm; soamodule soap; workhouse
• "逻辑" 英文翻译 :    logic 有学问而且合逻辑地辩论 argue with learning and logic; 逻辑上的错误 an error in logic; 数理逻辑 mathematical logic; 合乎逻辑 logical; 按照这种逻辑 according to that kind of reasoning; 这是什么逻辑 ? what sort of logic is that?; 逻辑包含 logical inclusion; 逻辑比较 logic comparison; logical comparison; 逻辑变换 logical conversion; 逻辑变量 logic variable; 逻辑 (型)变量 logical variable; 逻辑变项 [数学] logical variable; 逻辑表 logical table; 逻辑表达式 logical expression; 逻辑差 logical difference; 逻辑常数 logical constant; 逻辑程序 logical program; 逻辑错误 logical error; 逻辑代数 logic algebra; boolean algebra; algebra of logic; 逻辑单元 logical block; logic unit; 逻辑电路 logic circuit; logical circuit; 逻辑段 logical segment; 逻辑范畴 logical categories; 逻辑方法 logical method; 逻辑方阵 logical square; 逻辑分析 logic analysis; 逻辑分析法 analysis; 逻辑符号 logic symbol; logical symbol; 逻辑赋值语句 logical assignment statement; 逻辑关系 logical relation; 逻辑规格 logical specification; 逻辑规律 logical laws; 逻辑规则 logic rules; 逻辑函数 logical function; 逻辑恒量 logical constant; 逻辑机 logical machine; 逻辑级 logic level; 逻辑计算机 logical computer; 逻辑记录 [自动化] logical record; 逻辑解释 logical interpretation; 逻辑经验论 [哲学] logical empiricism; 逻辑经验论者 logical empiricist; 逻辑矩阵 logic matrix; 逻辑卡片 logic card; 逻辑连接 logical link; 逻辑连接词 logical connective; 逻辑连接符 [数学] logical connectives; logical connector; 逻辑连结 logical connection; 逻辑矛盾 logical contradiction; 逻辑曲线 [统计学] logistic curve; 逻辑设备表 logical unit table; 逻辑设计 [自动化] logic design; logical design; 逻辑实证论 [哲学] logical positivism; 逻辑实证论者 logical positivist; 逻辑实证主义 logical positivism; 逻辑史 history of logic; 逻辑数学 logical mathematics; 逻辑思维 logical thinking; 逻辑特征 logical implication; disjunction; 逻辑条件语句 logical if statement; 逻辑图 [自动化] logic diagram; logical chart; 逻辑推演 logical deduction by reasoning; 逻辑网络 logical net (work); 逻辑文件 logical file; 逻辑项 logical term; 逻辑型 logical type; 逻辑形l grammar; 逻辑原子论 [哲学] logical atomism; 逻辑运算 logical calculus; logical operation; 逻辑障碍[心] paralogia; 逻辑哲学 philosphy of logic; 逻辑正确 logically true; 逻辑证明 logical proof; 逻辑值 logic value; logical value; 逻辑制表 logic tab; 逻辑重音 logical accent; 逻辑主义 logicism; logicistic; 逻辑主语 [语言学] logical subject
• "根模块, 段模块" 英文翻译 :    root module
• "abs模块" 英文翻译 :    abs module
• "camac模块" 英文翻译 :    camac module,
• "表模块" 英文翻译 :    table module
• "单模块" 英文翻译 :    single module
• "垫模块" 英文翻译 :    filler piece
• "读模块" 英文翻译 :    read through model
• "多模块" 英文翻译 :    multi-module
• "宏模块" 英文翻译 :    macro-blocks; macroblock; macros
• "活模块" 英文翻译 :    loose piece
• "假模块" 英文翻译 :    dm dummy module

• Each logic module was verified by simulation
  通过仿真，验证了各个模块逻辑设计的正确性。
• A complete vvp instrument consists of one enhanced main board and several plug - in boards , which is suitable for constructing basic instruments ( no cpu ) , typical instruments ( a single cpu ) and advanced instruments ( multi - dsp )
  本章详细阐述了vvp平台的设计思想、体系结构以及vvp控者模块逻辑设计的实现。
• Simulations are executed in altera ’ s quartus ii environment with altera ’ s stratix family fpgas using verilog hdl after analysis . the results show that the sfn adapter can properly insert mip into transport stream and the time to be delayed in sync system can be correctly calculated and carried out with fifo
  在对每一个模块的设计要点做了详细说明之后,采用verilog语言编写各模块逻辑代码,在altera公司的quartusii5 . 0集成开发环境下,基于altera公司stratix系列fpga对各模块及整个单频网适配器进行了仿真。
• Concretely , on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ) , the standard and the module application of dsp and cpld , the thesis has proposed the design of the arinc 429 technology based on dsp system . at first , the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced . secondly , the hardware structure of the interface module is described in detail , mainly including data latch and buffer circuit , choice circuit of transmission rate , etc . and then the design philosophy and flow charts of the software are fully discussed , such as the basic requirement of software , the design and realization of the function
  本文在简单的论述了pc并口协议( epp )与dsp之间的通信方法、 cpld模块逻辑控制应用和arinc429的通讯规范的基础上,给出了基于dsp的arinc429通讯接口的设计方案:对通讯板中各模块的功能和应用以及构成数据转换主体的总线接口芯片hs - 3282的工作原理做了说明;介绍了本设计所用的dsp和cpld的功能概况;详细叙述了通讯板接口模块的硬件结构设计,其中,对数据缓冲电路、数据传输速率选择电路、逻辑控制电路等各关键点做了重点介绍;具体阐述了软件设计思想及流程图,包括软件的基本要求和功能的设计与实现;接着从端口译码单元、 i / o通道、电平转换电路等方面进行了接口模块的软、硬件调试;最后,给出了测试结果,对研制工作做了总结,对本设计的优缺点各做了评述。
• According to the function of test platform , the test platform is partition into a few modules . those modules are designed with verilog hdl and the key problems are discussed in details . the verilog codes for transmit and receive end of test platform are simulated under quartus ii 5 . 0 ise , and debugged by downloading the verilog programs into ep1s25f780c and ep1s80b956c6 developing kits
  在对每一个模块的设计要点做了详细说明之后,采用verilog语言编写各模块逻辑代码,在altera公司的quartusii5 . 0集成开发环境下,基于altera公司stratix系列fpga对各模块及整个窄带ldpc解码-误码测试平台进行了仿真并将发端和收端的verilog程序分别下载到altera的ep1s25f780c和ep1s80b956c6开发实验板进行调试。