流水线结构的英文

• pipeline organization

• "流水线"英文翻译    flow line; assembly line; pi ...
• "结构"英文翻译    structure; composition; cons ...
• "流水线数字结构" 英文翻译 :    pipelined digital architecture
• "算法结构流水线" 英文翻译 :    algorithm-structured pipeline
• "流水线" 英文翻译 :    flow line; assembly line; pipeline; stream-lined line◇流水线操作 pile line operation; 流水线控制 pipeline control; 流水线生产 [工业] flow-line production; continuous line production; 流水线系统 pipeline system; 流水线装配法 progressive assembly
• "标量流水线" 英文翻译 :    scalar pipeline
• "不变流水线" 英文翻译 :    fixed assembly line
• "操作流水线" 英文翻译 :    operation pipeline
• "超流水线" 英文翻译 :    superpipeline
• "成型流水线" 英文翻译 :    assembling conveyer system
• "地址流水线" 英文翻译 :    addre pipe; address pipe
• "纺丝流水线" 英文翻译 :    thread-line
• "过程流水线" 英文翻译 :    process line
• "焊接流水线" 英文翻译 :    welding streamline; weldingstreamline
• "宏流水线" 英文翻译 :    macro pipeline; macropipeline
• "活动流水线" 英文翻译 :    active pipeline
• "加工流水线" 英文翻译 :    process line
• "可变流水线" 英文翻译 :    variable assembly line
• "空罐流水线" 英文翻译 :    can bleeding
• "流水线变换" 英文翻译 :    pipeline transform
• "流水线操作" 英文翻译 :    pile line operation; pipe line operation; pipeline operation; stream line operation; streamline operation
• "流水线处理" 英文翻译 :    pipelining processing; pipeliningprocessing
• "流水线段" 英文翻译 :    pipelining segment
• "流水线法" 英文翻译 :    pipelining
• "流水线方式" 英文翻译 :    pipeline fashion; pipeline system

• Second , this dissertation gives an algorithm of object - based fast warping
  然后论文提出了一种流水线结构的基于对象模型的快速warp变换算法。
• The crucial trait of risc architecture is that it can fit the pipeline compatibly
  Risc体系结构的重要特点是其便于利用流水线结构进行指令操作。
• By analyzing the realization of range migration , we conclude that the pipeline structure is effective to implement azimuth processing
  通过分析距离迁移校正环节的实现过程，提出用流水线结构完成方位处理并且在并行处理平台上实现。
• Fixed - quatity emu1ation with standard program proves that the construct of the pipeline is with reason , and indicates that the average speedup of the pipeline is 1
  典型程序定量仿真测试证明了该流水线结构的合理性，流水线的平均加速比在1
• This paper introduces the history of the gpu firstly , and then it analyses the pipeline architecture of gpu . finally , it introduces several types of program languages of gpu
  本文首先介绍了可编程图形硬件的发展，然后分析了它的流水线结构，最后介绍了几种最新的编程语言。
• On the basis of designing the serial structure of mq encoder , parallel structure of mq encoder is designed using pipelining technique and the coding rate is approximately 1bit / cycle
  为了得到更高速率的mq编码器,采用流水线结构设计了并行的mq编码器。仿真结果表明mq编码器的编码吞吐量明显提高,达到了硬件规模和编码效率的平衡。
• The armp , which is controlled by a pipeline mechanism , has excellent real time performance and supports precise interrupt . the armp is compatible to powerpc 603e instruction set architecture ( isa ) , and will be implemented by 0 . 25 m cmos technique
  该处理器具有自主版权，采用自主设计的流水线结构进行控制，具有优良的实时性和精确中断的特点，在指令集上与powerpc603e指令集完全兼容。
• For fast computation of dynamic equations , a special operation unit is referred according to the computing structure of dynamic equations . the pipeline idea is used in this operation unit . there are a adder , a multiplier and a trigonometric function generator in it
  在动力学方程的快速计算方面，根据动力学方程的计算结构提出一种可用于专门计算机器人动力学方程的运算单元，此运算单元采用流水线结构，其运算部分包括加法器、乘法器和一个三角函数发生器。
• During the design of vxi - bus serial controller module , the functions of vxi - bus including time - sequence for vxi interface , resource management , interrupt process , bus arbitration , are accomplished . to advance the performance and stability , the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence , the uart , the parameterized baud generator and “ pipeling frame ” . the handle type of data transfer bus for vxi - bus is researched thoroughly , and the format of serial data transfer is designed
  在vxi总线串行控制器设计中,实现了vxi总线控制器的基本功能,包括vxi总线接口时序、总线仲裁、超时处理等;同时利用先进的fpga技术实现了串行总线时序向vxi总线时序的转换、通用异步收发器( uart ) 、参数化波特率发生器、流水线结构等功能模块;在设计中还深入研究了vxi总线数据传输的各种操作类型,制定了串行数据传输的编码格式。
• ( 2 ) research the instruction launch strategy , controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline . obtained the design modes : static launch , optimized compile instruction , 1st pipeline jump and branch processing and double pipeline four channels front data path . ( 3 ) achievement designs by the platform xilinx ise 5 . 2i , uses the verilog hardware description language to carry on the design description to the double - launching
  ( 2 )对基于32位mips架构双发射流水线的指令发射策略、控制相关处理和数据相关处理等流水线结构的重要问题进行深入研究,并得出了静态发射、优化编译指令序、第一流水线无延迟分支处理和双流水线四通道前向数据通路等一系列能够与32位mips架构相匹配的双发射流