logic synthesis中文是什么意思

• 逻辑合成
• 逻辑综合

• logic    n. 1.逻辑，理论学。 2.推理[方法]；逻辑性，条理 ...
• synthesis    n. (pl. -ses ) 综合，【化学】合成；【逻辑 ...
• synthesis, logic    逻辑合成
• synthesis of threshold logic    阈逻辑综合
• threshold logic synthesis    阈逻辑综合
• for synthesis    合成用
• synthesis    n. (pl. -ses ) 综合，【化学】合成；【逻辑学】综合(法)；【语言学】综合(性)；语词的合成；【医学】接合；【物理学】合成综合。
• -logic    -logic, -logical 〔构成与 -logy 结尾的名词相应的形容词〕表示“…学的”： biological, philological.
• and logic    “与”逻辑
• logic    n. 1.逻辑，理论学。 2.推理[方法]；逻辑性，条理性。 3. 威力，压力，强制(力)。 deductive [inductive] logic演绎[归纳]逻辑。 dialectical logic辩证逻辑。 formal logic形式逻辑。 a gangster logic强盗逻辑，恶徒的歪理[言行]。 mathematical logic数理逻辑。 pure logic纯粹逻辑。 He is not governed by logic. 他没有逻辑性。 That is not logic. 那不合逻辑。 the irresistible logic of facts 事实的不可抗拒的威力。 the logic of events [war] 事件[战争]的强制力。 His logic is shaky. 他的推理站不住脚。 chop logic 诡辩。
• logic-and    逻辑“与”
• or logic    或逻辑
• abiotic synthesis    非生物合成
• active synthesis    有源综合
• additive synthesis    附加合成
• admittance synthesis    导纳综合
• alfene synthesis    铝烯合成法
• alfol synthesis    铝醇合成法
• alternative synthesis    别种合成法
• amidine synthesis    脒合成
• ammonia synthesis    氨的合成; 氨合成法; 合成氨
• analog synthesis    模拟综合
• analysis and synthesis    分析和综合; 分析与综合
• analysis by synthesis    综合分析
• anodic synthesis    阳极合成

• The fourth chapter is the implementation part of carrier recovery in asic , including structure division , hardware design logic synthesis and verification . the asic design skills oriented to synthesis and dft ( design for test ) are discussed in the end
  第四章给出载波同步在asic设计中的具体实现，包括结构划分、硬件设计、逻辑综合和验证等，最后讨论了面向综合的asic设计技巧和可测性设计。
• Except for design methodology and technique , some comprehensive experiments are performed . these experiments use some eda tools , including functional simulation with cadence ' s verilog xl , logic synthesis with synopsys ' s design compiler
  本文除了介绍的设计方法和设计技巧，还做了一些有益的实验，使用到许多流行的eda工具，如cadence公司的verilog - xl 、 siliconensemble ， synopsys公司的designcompiler 、 physicalcompiler等。
• High - level synthesis has been developed on the base of logic synthesis . it starts from the behavioral design description of high - level and outputs the structural description with lower level as a result . so the design complexity can be simplified and design efficiency can be raised
  高级综合是在逻辑综合的基础上发展而来的，它从高层次的行为描述开始，自动综合出低层次的结构描述，从而降低了设计复杂度，提高了设计效率。
• This paper focuses on the combitional logic synthesis including two level logic synthesis and multiple level synthesis . and it is a part of control flow synthesis in a controller synthesis system . in this paper following problems are proposed and implemented : ( 1 ) implement the algorithm " espresso " , and make it suit to the system
  本文所完成的组合逻辑综合的研究与实现是控制流综合系统的一个组成部分，其中包括： ( 1 )引入并实现了两级逻辑综合的“ espresso ”算法，定义与系统相适应的数据结构，重新测试各种开关条件，使之适用于系统的实际应用。
• 26th ieee asilomar conference on signals , systems , and computers , pacific grove , ca , usa , october 26 - 28 , 1992 , pp . 391 - 395 . 14 oklobdzija v . an algorithmic and novel design of a leading zero detector circuit : comparison with logic synthesis . ieee transactions on vlsi systems , 1993 , 2 : 124 - 128
  而另一方面，该算法与目前国际上其它类似算法相比具有面积和功耗上的明显优势，根据实验结果，采用该算法所实现的电路面积比采用以往类似算法所实现的电路面积减少了27 ，功耗则降低了28 ，因此特别适合在高性能低功耗的浮点加减运算算法中采用。
• There ’ re two parts in the thesis : the design and implementation of fpga module and the design and implementation of the aes digital audio i / o circuit . i use xilinx corporation ’ s ise4 . 2 as development tools to carry on fpga design , including hdl coding , functional simulation , logic synthesis , place & route and generation of programming files . fpga is used to implement audio routing , sine wave , adc ’ s calibration and led etc , . also , i have downloaded the configuration program into fpga chipset using mcu . eventually , the device is tested and the requirements of design is met
  通过测试, etheraudio音频路由器完全达到了设计要求。 etheraudio音频路由器完全符合aes / ebu硬件规范,满足专业音频传输、路由需求。最后,本文还介绍了etheraudio音频路由器在广播电台中的应用实例,通过分析该音频路由器在广播电台的应用方式说明本课题的实际应用价值。
• At the logic synthesis stage , we make some research on the principles of logic synthesis at first , then by utilizing tsmc0 . 25um process , choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2 . 25v , and introducing the wireload library for effectively simulating delay and power consumption of wire connection , and taking the same clocks as in simulation , the critical path is 15 . 3ns and the chip area is 0 . 395mm2
  在进行逻辑综合时首先对逻辑综合的原理作了一定的了解，然后利用tsmc的0 . 25 m的工艺库，工作电压为2 . 25v ，工作温度最高可达到125摄氏度的最坏情况下，进行逻辑综合时引入了wireload库以便有效的模拟连线所引起的延迟及功耗，采用与模拟时相同的时钟，关键路径为15 . 3ns ，芯片面积为0 . 395mm ~ 2 。
• It ' s suitable for the design of chips that has high performance and large needs . the approach includes system design , logic synthesis , simulation , placement and routing , and etc . as an example , the design process of an asic for frequency measuring is discussed detailed to show how to use this approach quickly and successfully
  该方法包括系统设计、逻辑综合、仿真、布局布线等top - down的asic设计步骤。论文以asic测频芯片的设计过程为例，详细分析讨论了定制法的各个设计环节，以实际的设计过程论证各个设计环节，并且解决了在各个设计环节中遇到的问题：可测性设计的考虑、布局布线的考虑等。
• This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
  该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。
• This paper first discusses the feature of vhdl , and introduces the process of very long digital system by vhdl and auto - synthesis system with the method of top - down through designing control system of color lamp , reveals that it is very important to design digital system , logic synthesis and emulation with vhdl
  本文介绍了硬件描述语言的功能特点，并通过彩灯控制系统的设计过程（给出了仿真结果） ，介绍应用硬件描述语言及自动综合系统以自顶向下的方法进行大规模数字系统设计的过程，揭示了硬件描述语言设计数字系统、逻辑综合和仿真等技术在数字系统设计中的重要地位和作用。

• logic synthesisとは意味：論理合成｛ろんり ごうせい｝