design vt. 1.计划,企图,立意要…。 2.指定,预定;留给,留着。 3.设计,草拟,拟定,筹划;起草,画草图,打(图)样。 design an attack 计划进攻。 design one's son for [to be] a soldier 立意要儿子做军人。 design a room for one's library 指定一间屋子做某人书房。 vi. 计划;打样,打图样 (for)。 n. 1.计划;企图;目的,意图,野心,阴谋。 2.(小说等的)提纲,结构,构想,情节。 3.设计,图案,图样。 by design and not by accident 是故意不是偶然。 have a design on 对…有野心,企图。 have designs upon [against] sb.'s life 拟加害某人。
This thesis focuses on low power research on the high performance general - purpose processor design , which is based on godson - 2 processor core . many creative methods are raised in this paper . the following is the main contributions of this thesis : 1 本文针对当前高性能通用处理器设计,结合龙芯2号高性能通用cpu的研制,对高性能通用处理器核的低功耗技术进行研究,提出了一系列实用有效的低功耗技术和方法。
The author of this paper attended the project of risc / dsp processor design - md32 , which is development by the department of information science and electronic engineering in zhejiang university , and studied the design methods of isa and microarchitecture . md32 isa is a novel architecture , which features with both risc and dsp 本文作者参加了浙江大学信息与电子工程学系socr & d小组承担的国家863超大规模集成电路设计重大专项项目,参与开发了具有自主知识产权的risc dsp处理器? ? md32 ,并从中总结出结构、微结构设计等方面的一些方法和理论。
Then , put forward the design policy for the lower - layer of embed linux browser . considering running on embed system platform , each blocking i / o operation has been encapsulated to be independent module by using “ request queue - asynchronous callback ” mechanism implemented from command processor design pattern 针对嵌入式平台的特点,利用根据命令处理器设计模式实现的“请求队列-异步回调”机制,将各个引起延迟的网络i / o操作模块封装隔离成可以异步回调操作的模块。
So we decide to develop a vliw microprocessor of our own . secondly , four key problems in vliw processor design are studied , including how to exploit enough ilp , code compatibility , vliw formation , and the cell oriented instruction sets , and then the microarchitecture of the target vliw microprocessor is decided 本文接着研究了vliw处理器设计的五个关键问题:如何充分开发ilp 、代码兼容性问题、 vliw的格式、元操作面向何种指令集和vliw处理器的微体系结构,并在对这些问题现有的主要解决方案作了分析对比后,确立了目标vliw处理器的设计指标。
Even a recent scandal involving a top chinese computer scientist dismissed for copying an american processor design came to light in part because of internet hunting , with scores of online commentators raising questions about the project and putting pressure on the scientist ' s sponsors to look into allegations about intellectual property theft 甚至最近一个关于一位顶级的中国电脑工程师由于抄袭了一位美国专家的设计而被解职的传闻因网络追杀而被部份暴光,大量在线评论者提出了关于这个项目以及通过给这位工程师的赞助者施压来应对关于智力性质偷窃的断言的疑问
The radar intercept system signal processor designing issues are also discussed in chapter 6 . an architecture of signal processor is brought forward , while several examples support it . the advantages of real time operating system ( rtos ) are illustrated , and the approach to develop signal processor software infrastructure is probed into . at the end of thesis , the parellel design problem is summarized 信号处理器设计是雷达截获系统工程实现领域无法回避的问题,论文第六章在大量工程实践的前提下,提出了雷达截获系统信号处理器设计的基本结构模型;对实时操作系统应用于处理器软件平台设计的必要性和可行性进行了分析;还对处理器的并行设计技术进行了探讨。
In this dissertation , several technology problems of pulse trains deintrleaving algorithms are dealt with , they are presorting techniques based on coherent processor , probabilistic neural network deinterleavers , adaptive data association methods for pulse trains analysis and deinterleaving , signal processor designing issues . the research is focused on real time processing . the coherent processor is a crucial technique for real time presorting 本论文研究高密度复杂信号下的脉冲列去交错技术的若干问题,包括基于关联比较器的信号预分选技术研究;概率神经网络脉冲去交错器的研究与设计;卡尔曼滤波和概率数据关联方法用于脉冲列分析和去交错;雷达截获系统信号处理器设计等等。
High performance general - purpose processor design is the key technology of current vlsi design . as vlsi technology developing rapidly in complexity and density , power consumption of chips has become a major concern in the state of art high - performance cpu design . this problem has been even a main challenge to moore ’ s law 处理器芯片的功耗不但在很大程度上影响着处理器的性能、封装、测试以及系统可靠性等,还在很大程度上决定着片上系统以及未来多核处理器设计的发展方向,功耗问题开始成为阻碍目前高性能通用处理器深入发展的最主要因素之一,甚至被业界人士认为是对摩尔定律的一大挑战。