Internal scan is advanced for the difficulty of fixing the state of sequential circuit , can be divided into full - scan and partial - scan . in this paper we use full - scan according to the real circumstance of estarl and get high fault coverage with very little impact on the circuit 本文根据estar1的实际情况,设计实现了全扫描结构,既得到了较高的故障覆盖率,又对电路的延迟和芯片面积影响很小(延迟时间增加0 . 3 ,芯片面积增加0 . 01 ) 。
Test vector generation based on ant algorithm is presented and implemented , the pheromone computation formula for sequential circuits and status transfer rules are given , and the test results are compared with the results of the other existing test generators - hitec , gatest , cris , digate and strategate , based on standard sequential circuits iscas ' 89 and other synchronous sequential circuits 提出并实现了基于蚂蚁算法的测试矢量生成,给出了针对时序电路测试矢量生成的信息素计算公式和状态转移规则。在iscas ’ 89标准时序电路和几个同步时序电路上实现了测试生成,并将生成结果和其它现有测试生成器( hitec , gatest , cris , digate , strategate )的生成结果作了比较、分析。
Most of the circuit structures met in calendar schematic and the fundamental idea of analysis and design of the sequential circuit are discussed in this paper and the operation principle and the design method are analyzed from two points , one is the circuit theory of all the modules , the other is how the whole system works . the paper also expounds the design method - and the design flow of the 1c by the numbers through real examples 本文详细讨论了万年历电路分析与设计中遇到的各种电路类型和时序电路分析设计的基本思想,从万年历各子模块的电路原理和整个系统如何运作两个角度深入分析了万年历电路的工作原理和设计思路,以实例系统地阐述了集成电路的设计方法与设计流程。
We first propose and implement a sequential word - level pattern parallel fs algorithrn for synchionous sequential circuits . differing from other similar algorithins , it utilizes the relative independence of every fault test sequence generated by the g - f two - value tg algorithm , pwtitions and dynamically mounts test pattem , avoids redundant simulation for added synchlronous sequence , and gets better results 首先提出并实现了一个新的同步时序电路单机字级测试码并行fs算法,该算法与现有同类方法的不同在于,利用确定性g - f二值tg算法的每个故障测试序列之间的相对独立性,对测试码进行分解并动态组装,避免了对添加的同步序列的冗余模拟,效果较好。
Flip - flop is the core of sequential circuits , this dissertation designed a synchronous set - reset edge - trigged jk flip - flop based on rt quantum devices , the jk flip - flop has strong function and high speed , and also riches the types of flip - flops in quantum circuits 所设计的jk触发器功能强,且与传统的触发器相比,基于rt量子器件的边沿型jk触发器具有量子器件的功耗低、速度快、电路简单等特点。本文设计的jk触发器丰富了量子电路中触发器的种类,使得量子时序电路的设计更为灵活。
Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed . compared with tranditional methods , it is not too optimistic or pessimistic , fit for the exact timing of high - speed circuit design 在时序逻辑电路精确定时方面,从时序电路的敏化定理出发,使用本文给出的条件可敏化概念,通过对通路敏化性质的判断建立了一种新的单周期敏化的时序电路最小时钟周期精确确定方法。
Some theoretical extensions are first made in this paper , with the following concepts , theorems and models presented - partial derivative and high - order partial derivative of waveform polynomial for describing the relation between input transitions and output transitions and redefining circuit sensitization ; the concept of waveform polynomial vector for describing a circuit with multiple inputs and outputs , especially for the unified description of circuit modules ; a sensitization theorem for sequential circuits for the purpose of exact timing ; theorems for transition numbers in circuits used to solve problems on noise , power consumption and etc ; waveform polynomial description for sequential circuits used to give a unified form for the function and timing behavior of a sequtial circuit ; and a data structure of generalized list for the representation and manipulation of waveform polynomial 波形多项式偏导和高阶偏导的新概念,用来精确描述输出跳变与输入跳变之间的关系,并在本文中用来重新定义了电路的敏化和冒险;波形多项式向量的概念,用于形式化描述实际中的多输入多输出的电路,特别是用于统一描述电路模块的功能及定时行为;时序电路的敏化定理,用于时序电路精确定时分析;波形多项式描述跳变及跳变数的定理,用于噪声、功耗等问题的描述;时序电路的完整波形多项式描述,用于时序电路功能和定时行为的统一描述;波形多项式的多项式符号表示和运算的模型以及数据结构,用来实现对波形多项式比较有效的描述和运算。