硬件语言的英文

• hardware language

• "硬件"英文翻译    hardware
• "语言"英文翻译    language
• "数字硬件语言" 英文翻译 :    digital hardware language
• "条件语言" 英文翻译 :    conditional statement
• "开放文件语言" 英文翻译 :    odl
• "应用软件语言" 英文翻译 :    application software language
• "中间文件语言" 英文翻译 :    neutral file language
• "硬件描述语言" 英文翻译 :    hardware description language (hdl); hdl hardware description language; language, hardware description (hdl)
• "硬件设计语言" 英文翻译 :    hardware design language
• "虚拟代数式操件语言" 英文翻译 :    ghost algebraic manipulation language
• "vhsic硬件描述语言" 英文翻译 :    vhsic hardware description language
• "可视硬件描述语言" 英文翻译 :    vhdl visual hardware des cription language; vhdl visual hardware description language
• "模拟硬件描述语言" 英文翻译 :    analog hardware description language (ahdl); language, analog hardware description (ahdl)
• "视觉硬件描述语言" 英文翻译 :    vhdl visual hardware description language
• "输入硬件描述语言" 英文翻译 :    ihdl input hardware des criptive language; ihdl input hardware descriptive language; input hardware descriptive language
• "硬件程序设计语言" 英文翻译 :    hardware programming language
• "计算机硬件定义语言" 英文翻译 :    computer hardware definition language
• "计算机硬件描述语言" 英文翻译 :    chdl computer hardware description language; computerhardwaredescriptionlanguage
• "硬件设计语言与原型化" 英文翻译 :    i ii iii ece hardware design language and prototyping
• "硬件" 英文翻译 :    hardware 计算机硬件 computer hardware
• "超高规模集成电路硬件描述语言" 英文翻译 :    ion language (vhdl); language, vhsic hardware description (vhdl); vhsic hardware description language
• "超高速集成电路硬件描述语言" 英文翻译 :    vhdl vhsic hardware des cription language
• "甚高速集成电路硬件描述语言" 英文翻译 :    vhdl very high speed integrated circuit hardware description language
• "fortran条件语句" 英文翻译 :    fortran if
• "构件语法" 英文翻译 :    component grammar

• The thesis is a research of the pic microcontroller of microchip corporation . the thesis includes a design of a cpu ip core with verilog hdl , and the design bases on up - down design flow
  首先从正向设计和仿真的角度，给pic微控制器中的核心部件-处理器单元建立了一个硬件语言描述的ip模型。
• The aim of this paper is to implement the decoder of turbo codes with fpga . the iterative decoding algorithms and how to implement them with hardware language have been discussed in the paper
  本文以turbo码译码器的fpga实现为目标,对turbo码的迭代译码算法及用硬件语言实现其译码算法进行了深入研究。
• The second part studies the characteristics of cdma2000 1x reverse link , and implements a softcore design of the cdma20001x rtl soc with hdl ( hardwire desciptionin language ) verilog in accordance with the is - 2000 specifications . the model include the softcore of a spread spectrum modulation and a simple 8 - bit processor . as the same time simulate all the parts of the soc softcore with software modesim
  ，本文的第二部分认真的研究了cdma20001x的反向链路的特点，设计反向链路的扩频调制片上系统方案。用硬件语言verilog设计cdma20001x的扩频调制片上系统的ip软核。其中包括扩频调制部分和一个8位的cpu设计。
• This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
  该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。
• We choose the max _ log _ map decoding algorithm and use the technology of altera and its cyclone2 devices as the fpga design scheme according to all the factors . taking advantage of the technology of fpga , the means , called “ top - down ” and “ down - top ” , is applied in the design of fpga in this paper
  在综合考虑设计方案的综合性能、复杂程度、系统规模、系统延时和成本等各项因素后,本次设计选择了altera公司的cyclone2器件来完成turbo码译码算法( max _ log _ map )在硬件语言上的仿真设计。
• The vxibus c - size and i , q channels are employed in this module design , and the sampling rate in each channel reaches 500mhz . the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ) . the timing and logic function are fulfilled by fpga . after the disscusion of signal adjusted , the detailed scheme of this module design have been showed . in this design , there is much logic function design , and it is very strict with the hardware language program . so the basic flow of hardware program design and several very important methods of high speed logic function design , which is described by vhdl , are introduced . also , expatiated the inner modules structure of fpga for forepart circuit , the keystone and difficulties of the design . the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system , and it is very important . the timing simulating results of several pivotal modules are depicted . high - speed signal paths are terminated to match the characteristic impedance . the design undergoes integrity analysis and software simulation
  在本模块的设计中,有着大量的逻辑设计,对硬件语言程序的编写要求比较高,因此,文中介绍了硬件程序设计的基本流程,以及几种基于vhdl硬件语言设计在高速逻辑设计中非常重要的方法。同时阐述了本模块设计的前端fpga的内部模块结构,设计的重点、难点,并给出了重要模块的时序仿真结果。高速pcb的设计也是目前实现高速数据采集系统的难点和重点,文中详细的阐明了高速pcb设计中的注意点,以及作者在设计本模块时的经验和心得。